Static random access memory (SRAM) cells have occupied a large portion of the Large Scale Integrated (LSI) device chip market as higher volume memory has become a desired feature. However, as further chip developments are made, enhancing performance and stability of SRAM cells remains an important factor.
To improve performance and stability of SRAM cells, channel widths and lengths are adjusted to produce a high SRAM yield. However, this method has become less effective when producing high density SRAM cells because pull-down field effect transistors (FETs) with wide channel width and pass-gate FETs with wide gate length increase SRAM array size. In addition, non-constant gate pitch degrades the lithography margin. As a result, gate length variation becomes large, which degrades SRAM stability. Further, constantly adjusting channel widths and lengths makes cell design more difficult across a chip. Finally, doping agent out-diffusion and/or process induced stress tend to cause unexpected electrical behavior in SRAM FETs. Therefore, actual on current ratios may be altered from the design ratio, thereby making circuit design difficult.